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Lattice Semiconductor
10Gb Ethernet XGXS IP Core User’s Guide
The random /A/, /R/, /K/ sequence is generated as speci ? ed in section 48.2.5.2.1 of IEEE 802.3ae and shown in
the state machine diagram in Figure 7. In addition to idle generation, the state machine also forwards sequences of
||Q|| ordered sets used for link status reporting. These sets have the XGMII sequence control character on lane 0
followed by three data characters in XGMII lanes 1 through 3. Sequence ordered-sets are only sent following an
||A|| ordered set.
The random selection of /A/, /K/, and /R/ characters is based on the generation of uniformly distributed random
integers derived from a PRBS. Minimum ||A|| code group spacing is determined by the integer value generated by
the PRBS (A_cnt in Figure 7). ||K|| and ||R|| selection is driven by the value of the least signi ? cant bit of the gener-
ated integer value (code_sel in Figure 7). The idle generation state machine speci ? ed in IEEE 802.3ae and shown
in Figure 7 transitions between states based on a 312MHz system clock. The TX encoder implemented in the
XGXS IP runs at a system clock rate of 156MHz. Thus the XGXS state machine implementation performs the
equivalent of two state transitions each clock cycle.
The ? nal stage in the programmable core is the transmit demultiplexer, which converts the 72 bits of data and con-
trol clocked at 156MHz to a 144-bit wide bus clocked at 78MHz, which is then passed to the ORT82G5 embedded
core. Data and control are distributed across the four XAUI lanes as discussed previously. The transmit data bus
per lane is 36 bits wide at the embedded core boundary as compared to the receive data bus which is 40 bits wide.
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